1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
Semiconductor devices so far developed include those disclosed in Patent Document 1 and Non-patent Documents 1 to 3 cited below. All the semiconductor devices described therein include a MIM (Metal Insulator Metal) capacitor as a capacitor element. In those semiconductor devices, an etching stopper layer serves as an insulating capacitor film.
(Patent Document 1) Japanese Laid-open patent publication No. 2003-324153
(Non-patent Document 1) Peter Zurcher et al., “Integration of Thin Film MIM Capacitors and Resistors into Copper Metallization based RF-CMOS and Bi-CMOS Technologies”, Electron Device Meeting 2000, IEDM Technical Digest, International 10-13, December 2000, p. 153-156
(Non-patent Document 2) M. Armacost et al., “A High Reliability Metal Insulator Metal Capacitor for 0.18 μm Copper Technology”, Electron Device Meeting 2000, IEDM Technical Digest, International 10-13, December 2000, p. 157-160
(Non-patent Document 3) C. H. Ng et al., “Characterization and comparison of Two Metal-Insulator-Metal Capacitor Schemes in 0.13 μm Copper Dual Damascene Metallization Process for Mixed-Mode and RF Applications”, Electron Device Meeting 2002, IEDM '02 Digest, International 8-11, December 2002, p. 241-244
FIG. 11 is a schematic cross-sectional view showing the semiconductor device according to the Patent Document 1. The semiconductor device includes an insulating interlayer 103 formed on a semiconductor substrate 101 via an etching stopper layer 102. The insulating interlayer 103 includes copper interconnects 106A, 106B buried therein, and the copper interconnect 106B serves as a lower electrode for a capacitor element. Accordingly, the insulating interlayer 103 commonly includes a conductive layer (copper interconnect 106A) ordinarily working as an interconnect, and another conductive layer (copper interconnect 106B) serving as both the interconnect and the lower electrode.
On the insulating interlayer 103, an insulating interlayer 109 is provided via an etching stopper layer 108. The insulating interlayer 109 includes a via 115 connected to the copper interconnect 106A and an upper electrode 116, buried therein. Accordingly, the etching stopper layer 108 works not only as the etching stopper when the via 115 is formed, but also as an insulating capacitor film 113. The portion of the etching stopper layer 108 working as the insulating capacitor film 113, i.e. the portion interposed between the lower electrode and the upper electrode, is made thinner than the remaining portions, because of the etching process that reduces the thickness.
The semiconductor device according to the Non-patent Documents 2 and 3 includes a second etching stopper layer on an upper electrode, in addition to a first etching stopper layer that serves as an insulating capacitor film. Such second etching stopper layer is intended for use as the etching stopper when a via plug to be connected to the upper electrode is formed.